On-chip inductance modeling of VLSI interconnects

Abstract

At gigahertz frequencies, long interconnect wires exhibit transmission line behavior. Using copper and wider wires for major signal and power/ground lines, inductive impedance (j/spl omega/L) could become comparable to the resistive component of the wire (R). Due to the inductance, delay increases, over-shoot occurs, and inductive crosstalk can no longer be ignored. Inductive effects were recently demonstrated in 4 mm-long lines in a 0.25 /spl mu/m process. The extracted delays of a typical clock line from this test chip are shown. While the delay is a linear function of line length, the RC delay increases with the square of the line length. As a result, the inductive effects are actually more prominent for lines with intermediate lengths. The inductive effects for the intermediate length buses as well as local clocks must be considered. As technology is scaled, the gate delay time will continue to be reduced while the delay of short, low-resistive clock lines will remain constant. The inductive effects will therefore become prominent for progressively short lines. The article shows simulated inductance effects on crosstalk. Larger coupling and ringing effects are observed when inductive coupling is included in the simulation. Currently, the inductive effects are only considered for a few global clocks and buses, which is insufficient for future designs. Although 3D electromagnetic full wave solvers are available, they cannot manage the complexity of today's integrated circuits. To model the inductive effects of intermediate-length buses as well as local clocks, a fast automated inductance extraction and verification tool is necessary.