Test architecture optimization algorithms for coarse-grain partitioned 3D system-on-chip

Abstract

The occurrence of manufacturing defects in complex 3D System-on-Chip can affect their performance and functionality. Massive test data is required to test such systems, which increases testing time. This paper presents an efficient heuristic-based solution that addresses test architecture development for both fixed and flexible design scenarios in coarse-grain partitioned 3D Systems-on-Chip. The algorithm minimizes the test times at inter and intra die levels while addressing the various constraints. It works in two stages: initially, it prepares a tentative test architecture for individual dies with fixed test widths. Later, a solution for the allotment of the test wires to separate dies is made such that the test time of the complete stack reduces. Experiments performed using different ITC’02 SoC benchmark circuits show the effectiveness of the proposed solutions. The resultant test time is comparable to the lower bounds of test time of the complete 2D benchmark.