Ternary Devices Based on Partially Aligned MoS2/h‐BN/Graphene Heterostructures

Abstract

AbstractThe development of multi‐valued logic devices, which involve switching between more than two states, is one of the promising approaches for overcoming the issues caused by the further scaling down of the current complementary metal‐oxide semiconductor devices. This paper presents ternary devices based on MoS2/h‐BN/graphene heterostructures, in which an active channel of MoS2 is partially aligned with a floating gate of graphene, unlike in the case of typical flash memory devices; thus, they can be regarded as a circuit consisting of a memory device and field‐effect transistor internally connected in parallel. The transfer curves of these devices exhibit two different threshold voltages (Vth) with ternary states (“0,” “1,” and “2”). Furthermore, the intermediate state can be controlled by oxygen plasma treatment, resulting in a ratio >102 for “1”/“0” states and “2”/“1” states. Thus, these devices can be used to implement a resistive‐load standard ternary inverter, whose output voltage is close to 1, 0.5, and 0 V under the supply voltage of 1 V. In addition, ternary NMIN and NMAX circuits with resistive loads are demonstrated by connecting two ternary inverters in series and parallel, respectively.