Temperature Impact on the Reset Operation in HfO<sub>2</sub> RRAM

Abstract

In this letter, we report about the impact of temperature on the reset operation in HfO 2 resistive random access memory (RRAM) devices. Standard I-V dc characterization (voltage sweeps) is exploited to separately assess the different temperature impact on reset and high resistance state (HRS) verify stages in real operating conditions. The temperature dependence of the processes involved in the two stages is obtained by extracting the effective activation energy of the charge transport in HRS verify, and exploiting a compact model for the reset stage. The compact model links I-V dc measurements to the physical properties of the dielectric barrier defining the HRS in the RRAM. A linear relation is found between barrier thickness and reset temperature. Results suggest that reset may be optimized with respect to the operating temperature to improve cycling variability, especially at ultralow reset voltages.