Temperature dependences of threshold voltage and drain-induced barrier lowering in 60 nm gate length MOS transistors

Abstract

The temperature dependence of threshold voltage (VT) and drain-induced barrier lowering (DIBL) characteristics for MOS transistors fabricated with three different threshold voltage technologies are studied. We found that the technique employed to adjust the VT value make the devices to be not well-scaled for short-channel effects for ultra-short devices at low temperatures. For devices with a short gate length (L<90nm) and being fabricated using the low threshold voltage (low-VT) technology, both the temperature dependencies of threshold voltage and DIBL are different to the standard-VT and high-VT ones. Abnormally large values of DIBL were found for low VT-devices because of the significant encroachment of drain depletion region on the channel region. On the other hand, the high substrate doping in high-VT process makes the devices to have a larger junction depth than that used in the standard process. It causes a poorer DIBL for short-channel devices. Hence the best scaling or design of the devices at room temperature does not imply that they should also be good at low temperatures, especially for L=60nm fabricated using the low-VT process. Different device design and process optimization are required for devices to be operated at temperatures beyond the nominal range.