Abstract
A new analytical model is presented for the temperature and bias dependence of the anomalous leakage current based on thermionic field emission via grain boundary traps in the gate-drain overlap region in polysilicon-on-insulator MOSFET's. The existing model based on pure field emission (tunneling) via grain boundary traps does not include a temperature dependence and therefore cannot explain the observed strong temperature dependence of leakage at low gate voltages, as well as the weaker temperature dependence at high gate voltages, which the new analytical model presented in this paper can. Below 150 K, we believe that impact ionization due to the increasing carrier mean free path leads to the observed increase in the leakage current with decreasing temperature. Since the analytical model does not include impact ionization, it cannot model the leakage current at low temperatures. >
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