TEM characterization of III-V semiconductors heteroepitaxially grown on Si substrates

Abstract

There has been considerable improvement over the last two years in the growth of III-V semiconductors on Si substrates, and some majority carrier devices such as FETs were reported using this technology. However, there are still a number of formidable problems to overcome in order to obtain high quality layers for minority carrier devices. Not excluding serious problems such as the large difference in thermal expansion coefficients, the effects of interface contamination and lattice mismatch were recognized by many workers to be the most adverse. In this work, these effects were investigated using conventional, analytical and high resolution TEM in an attempt to produce better quality epilayers. All layers were grown by MOCVD on (100) Si substrates misoriented by 2° towards (110). The TEM foils were prepared by a combination of mechanical polishing and I/Ar ion beam milling. This mixture of iodine and argon proved to be particularly valuable for milling InP/Si layers. To avoid the incongruent evaporation of phosphorous, the latter was performed at liquid nitrogen temperature using 15-20 μA beam current, 5KeV beam voltage and 12° incidence.