Technology of sub-100 nm InAlN/GaN HEMTs on silicon with suppressed leakage current

Abstract

Due to the thin InAlN barrier layer, leakage current is a serious problem in InAlN/GaN high-electron-mobility transistors (HEMTs). The InGaN back-barrier can raise the conduction band of the GaN buffer layer and enhance the carrier confinement, resulting in a reduced buffer leakage current. The surface oxidation treatment prior to gate deposition can form an oxide layer and reduce the barrier leakage current. In this study, using both technologies, a record low off current (Ioff) and a record high on/off current (Ion/Ioff) ratio are achieved on InAlN/GaN HEMTs on silicon substrate. The InAlN/GaN HEMT with a 70-nm rectangular gate presents a low Ioff of 7.15 × 10−8A/mm, a high Ion/Ioff ratio of 2.20 × 107, an average subthreshold swing (SS) of 69 mV/dec, and a low drain-induced barrier lowering (DIBL) of 90 mV/V. The InAlN/GaN HEMT with a 70-nm T-shaped gate exhibits a low Ioff of 3.26 × 10−8 A/mm, a high Ion/Ioff of 4.5 × 107, an average SS of 60 mV/dec, and a DIBL of 30 mV/V. To the best of our knowledge, these are record values among the reported InAlN/GaN HEMTs on Si. RF measurements present that current/power gain cutoff frequency (fT/fmax) of 215/45 GHz and 130/160 GHz are achieved on the 70-nm InAlN/GaN HEMTs with rectangular and T-shaped gate, respectively.