Abstract

GaN-based transistors with p-GaN gate are commonly accepted as promising devices for application in power converters, thanks to the positive and stable threshold voltage, the low on-resistance and the high breakdown field. This paper reviews the most recent results on the technology and reliability of these devices by presenting original data. The first part of the paper describes the technological issues related to the development of a p-GaN gate, and the most promising solutions for minimizing the gate leakage current. In the second part of the paper, we describe the most relevant mechanisms that limit the dynamic performance and the reliability of GaN-based normally-off transistors. More specifically, we discuss the following aspects: (i) the trapping effects specific for the p-GaN gate; (ii) the time-dependent breakdown of the p-GaN gate during positive gate stress and the related physics of failure; (iii) the stability of the electrical parameters during operation at high drain voltages. The results presented within this paper provide information on the current status of the performance and reliability of GaN-based E-mode transistors, and on the related technological issues.

Highlights

  • GaN-based high electron mobility transistors (HEMTs) are excellent devices for application in power electronics

  • When the transistor is in the off-state (condition (1) in Figure 1), a high drain-source voltage is applied to the HEMT

  • Gate,in weGaN-HEMTs discuss the following aspects: (i) thea pulsed of the technology devices, of HEMTs with gate, we discuss the to following aspects: the pulsed state-of-the-art and thep-GaN

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Summary

Introduction

GaN-based high electron mobility transistors (HEMTs) are excellent devices for application in power electronics. 2000 cm2 /Vs [2]) results in current densities around 1 A/mm, and in a very low on resistance (25 mΩ for a 650 V/60 A device [3]) This implies a significant reduction in the switching losses, with positive impact on the efficiency of GaN-based power converters. 1. When the transistor is in the off-state (condition (1) in Figure 1), a high drain-source voltage is applied to the HEMT. The high resulting field (Figure 2) may favor charge trapping mechanisms, including the filling/depletion of defects located in the C-doped buffer [6], the injection including the filling/depletion of defects located in the C-doped buffer [6], the injection of of electrons from the substrate [7], and surface trapping processes [8]. Schematic representation a boost power and converter and of the switching transitions during operation

Simulated
Normally-Off
Normally-off
Charge Trapping Processes Related to the p-GaN Gate
Degradation Processes Induced by High Drain Bias in the Off-State
Conclusions
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