Technologies for electron beam direct writing

Abstract

Development time of semiconductor devices which have a large volume of pattern data and fine feature size can be remarkably reduced by a high speed on-line system and an erase electron beam direct writing technology. Pattern data which is performed by a CAD system is converted by a VAX/780 and transmitted to an electron beam exposure system (EBES) through a communication controller at the speed of 1 Mbit/sec. Overlay accuracy less than 0.2 μm is obtained by scanning the alignment marks located at the periphery of a silicon wafer. The marks are fabricated by etching the silicon substrate to 2 μm depth. Radiation effects induced by electron beam irradiation is examined by Monte Carlo simulation. In production of ECL (emitter coupled logic) gate arrays using electron beam direct writing technology, the surface of the silicon nitride (SiN) interlevel insulation layer is coated with a thin conductive layer of TiW in order to avoid the charging phenomenon and the radiation damage caused by electron beam irradiation.