Abstract
Scan based transition tests are added to improve the detection of IC speed failures using scan tests. Empirical data suggests that both data volume and application time for transition test will increase dramatically. Techniques to address this problem, for a class of transition tests called enhanced transition tests, are proposed. The first technique, which combines the ATE repeat capability and the notion of transition test chains, reduces test data volume by 46.5%, when compared with transition tests computed by a commercial transition test ATPG tool. The test application time could increase or decrease. To address the test time issue, exchange scan, a new DFT technique, is proposed. Exchange scan reduces both data volume and application time by 46.5%. These techniques rely on the use of hold scan cells and highlight the effectiveness of hold-scan design to address test time and test data volume issues.
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