TCAD simulations of dual gate dopingless tunnel field effect transistor with spacer

Abstract

In this paper, the 2 D performance analysis of dual gate dopingless tunnel field effect transistor (DGDLTFET) with high dielectric material as a spacer using Sentaurus TCAD simulation tools is furnished. Doped TFET requires high doping which reflects high thermal budget in the fabrication process. To reduce the thermal budget in the process of fabrication dopingless TFET is chosen. The idea of charge plasma helps us for the formation of dopingless TFET source and drain domains by choosing the applicable work functions of the drain and source metal electrodes. In the proposed device, a 10 nm length of hafnium oxide (HfO 2 ) is used as a spacer, on both sides of drain and source regions, with a dielectric constant of 21.8 to avoid leakage of the carrier over gate edge. Spacer acts as an insulator to avoid leakage of the carrier over the gate edge. The simulation results of proposed device have lower sub threshold swing SS of 43.2 mV/decade Average SS of 51.8 mV/decade and a good I ON /I OFF ratio of 1011.