TCAD based study of a noble 24 nm DMIDG MOSFET for LOW power applications

Abstract

This paper presents the design of a noble 24 nm asymmetric Dual gate Material (for NMOS/PMOS) Independent Double Gate (DMIDG) with elevated S/D Structure, Buried Polysilicon Back Gate, High-K dielectric spacer, High-K gate stack of HfO 2 over SiO 2 thin layer (SiO 2 thickness being 0.85 nm while maintaining an EOT of 1.2 nm) at front gate in order to suppress SCE's. An IDG MOS device with metallic gate and lightly Doped Channel (of doping concentration of 2×109 cm−3) provides better leakage performance with the cost of effective high threshold voltage (0.56V for NMOS and −0.49V for PMOS), with symmetrical I D -V GS Characteristics and almost symmetrical I D -V DS characteristics for both NMOS and PMOS devices. The proposed devices are found to possess quite low Miller Capacitance (∼0.12 fF/μm for PMOS and ∼0.125 fF/μm for NMOS) with metallic front gate and lightly doped channel structure. The device also shows considerably low total gate capacitance as compared to ITRS Specification for LSTP application even in quasi Ballistic regime of channel length up to 12 nm. A CMOS inverter constructed using such DMIDG MOS devices shows quite low inverter delay of ∼ 4 psec. with back gate biasing of 0V for both PMOS and NMOS devices of channel length 24 nm. The delay Characteristics are also being modulated by favorable back gate biasing techniques. The inverter delay is found to be reduced following the technology downscaling and is close to ITRS Specifications. The dynamic energy consumption of the inverter is also low at favorable back gate biasing (of 0.5V for NMOS and −0.5V for PMOS) viz. 0.35 fJ/μm and it goes on diminishing as channel length goes on reducing. IDG MOS devices with metallic gate and lightly doped show better inverter characteristics in comparison to Polysilicon front gate and undoped channel devices.