TCAD-Assisted Capacitance Extraction of FinFET SRAM and Logic Arrays

Abstract

Technology computer-aided design (TCAD)-assisted automation of structure synthesis followed by a transport-analysis-based capacitance extraction approach has been shown to have a significant potential in the recent past in terms of both accuracy and efficiency. In this brief, we first propose three methods to speedup TCAD-assisted capacitance extraction of an SRAM array layout, by partitioning the layout into several fragments. We demonstrate that the speedup of these partitioning methods, relative to that of TCAD-assisted full-array capacitance extraction method, can be as high as $17\times $ , with an average of $3\times $ . On the other hand, the error in capacitance derived using the partitioning methods can be as low as 1.01%, with an average of 4.93%. We apply the partitioning methods to several layout configurations and styles of FinFET SRAM array layouts and demonstrate their efficacy. We then apply the partitioning methods to a ring oscillator, register, and two-bit adder, and demonstrate similar results.