Systolic Tensor Core for Arithmetics calculations

Abstract

Today, it is the amount of data that defines the existence of mankind. Scientists respond to the large amount of required calculations by developing hardware in several directions. One of them is to increase the number of arithmetic elements. Another direction is to create new architectures that represent new algorithms for processing numerical data. We have chosen the second direction by developing a new systolic core architecture, which implies an improvement in efficiency, i.e. performing the same task with the same number of arithmetic elements but reducing the latency. Measurements are made in terms of computational capacity and the number of arithmetic elements involved in the operations. The results of the tests are compared with data from a number of selected articles. Today, we have achieved 3.2GFlops with only two modules. In the future, we plan to integrate up to four of our cores in a system with its own memory and management processor and at a higher operating frequency.