Abstract
Counters are among the fundamental digital circuits in every computing system. For this reason, counter design is of great interest in the design of computers and embedded systems, in terms of area requirements, power dissipation and performance. Many techniques have been proposed in the past specifically to increase the counter's speed without increasing design complexity. Traditionally, it is of great concern to make a fast counter suitable for many applications, without adding to the critical path and keeping speed independent of its size. In this work, a binary counter is proposed, based on 1D Cellular Automata (CA), which is used as a prescaler in a systolic structure, that offers constant delay for counters of various bit-widths.
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