System-on-chip verification: TLM-to-RTL assertions transformation

Abstract

The Electronic System Level design flow aims to manage the great complexity of today's Systems-on-Chip: design and verification methodologies start from abstraction levels higher than RTL (Register Transfer Level), referred to as Transaction Level Modeling (TLM). At this level, virtual prototypes are used for early validation, software development, and as golden reference for the derived RTL designs. Assertion-based verification, a verification technique widely adopted for RTL designs, started to prove its efficiency at TLM. Verification is the bottleneck of the ESL design flow. Hence, there is a real need for a complete verification flow covering all the abstraction levels of the design flow. In this paper, we describe the implementation of an approach for temporal assertions refinement from TLM to RTL, using a set of transformation rules. The reuse of TLM assertions is the basis of an Assertion-based verification flow.