Abstract
Technology scaling continues to improve transistor performance and integration to realize complex systems and added functionality in SoC designs. This reduces the energy consumed with a 30% speed improvement per technology generation. The scaling, however, comes with some adverse effects posing perceived barriers. In this paper, we discuss the design challenges in Ultra Deep Submicron (UDSM) technologies and the scaling problems in SoC circuits for clocking and synchronization. This includes delay variations and functional errors due to various types of noise sources. Correct clocking and synchronization can be achieved through innovative strategies that work at all levels of abstraction.
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