System-Level Modeling of Microprocessor Reliability Degradation Due to Bias Temperature Instability and Hot Carrier Injection

Abstract

Negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), and hot carrier injection (HCI) are leading reliability concerns for modern microprocessors. In this paper, a framework is proposed to analyze the impact of BTI (NBTI and PBTI) and HCI on state-of-art microprocessors and to estimate microprocessor lifetimes due to each wearout mechanism. Our methodology finds the detailed electrical stress and the temperature of each device within a microprocessor system running a variety of standard benchmarks. Combining the electrical stress profiles, thermal profiles, and device-level models, we perform timing analysis on the critical paths of a microprocessor using our methodology to characterize the microprocessor performance degradation due to BTI and HCI and to estimate the lifetime distribution of logic blocks. In addition, we study dc noise margins in conventional 6T SRAM cells as a function of BTI and HCI degradation to estimate memory lifetime distributions. The lifetimes of memory blocks are then combined with the lifetimes of logic blocks to provide an estimate of the system lifetime distribution.