System-level design exploration for 3-D stacked memory architectures

Abstract

Traditional technology scaling of semiconductor chips followed Moore's Law. However, the transistor performance improvement will be limited, and designer will not see doubling of frequency every two years. Recently, three-dimension integrated circuits (3D IC) that employ the vertically through-silicon vias (TSVs) for connecting each of dies have been proposed. It is an alternative solution to existent Package-on-Package (PoP) and System-in-Package (SiP) processes. There are many benefits by using TSV-based 3-D integration technologies: (1) more functionality can be integrated into a small silicon space for form factor reduction, (2) circuit delay can be improved by using TSVs due to the shorter interconnect and reduced parasitic capacitance/inductance, (3) different components with incompatible manufacturing process (i.e. Logic, DRAM, Flash, etc) can be combined in single 3-D IC for heterogeneous integration. In addition, there are many 3-D multi-core or many-core architectures are discussed recently. Comparing with traditional two-dimension multi-core or many-core architectures, the major difference is memory bandwidth problem can be addressed by stacked memory architecture. Intel has good demonstration through the teraflops microprocessor chip which is an 80-core design with memory-on-logic architecture. And, each core connects to a 256KB SRAM with 12GB/s bandwidth. Although 3-D stacking technology can bring us many benefits for next generation integrated circuits, it comes with many problems and challenges in system-level design. For instance, 3-D IC designs will deal with serious challenges in design space exploration and system validation. For most designs, the number of TSV will be the most critical limitation that should be considered carefully. Besides, system design by 3-D IC will become more and more complex, and it needs a full system-level solution to face the performance, number of TSV, and power issues of 3D-IC. Furthermore, it is more challenge to provide a FPGA-based prototyping system for early-stage software development. In general, the continue increasing complexity of modern SoC or embedded system design is also extreme. To achieve the required design productivity for the time-to-market pressure, a common accepted solution is using electronic system-level (ESL) design methodology to design the system in the different design abstraction level. One of the key technologies of ESL solution is to construct the HW/SW co-simulation platform by using the virtual prototyping concept. Moreover, designers need a multiphase of virtual platform construction to meet the different targets of design stage, such as early system validation and architecture exploration. In this work, we create a simulation framework by using ESL methodology to explore 3-D IC system that consists of multi-core processors with extended stacking memory. To demonstrate our 3-D IC design techniques, the stacking memory approach is employed in our “3D-PAC (Parallel Architecture Core)” design. In 3D-PAC, we stack SRAM directly on top of the logic die which is heterogeneous multi-core computing platform for multimedia application purpose. The logic die is mainly consists of a general-purpose microprocessor, dual programmable digital signal processor (DSP) cores, AXI/AHB/APB subsystems, and various peripherals. Furthermore, we had the corresponding virtual platform (PAC Duo virtual platform) which had been used for early architecture exploration, power estimation and HW/SW co-simulation. The difference with PAC Duo design, the target of 3D-PAC is to provide a three-dimensional SoC (3-D SoC) design exporation for media-rich and multi-function portable devices. Although using the stacking memory approach with TSV technology can increase the capacity and performance of memory system significantly, but the placement and organization of the memory system are the nother important design issues. In this work, we use the ESL design methodology to consider these design issues for 3-D multi-core embedded system. According to our 3-D implementation, the number of TSV is additional important design constraint. The major issue is to find out the feasible system architect that can meet all the performance, power, area and TSV limitation design constraints. To achieve the requirement, we extend the virtual platform property to report the number of TSVs during the architecture exploration process. Besides, we also construct two kinds of virtual platform, one is using the approximately time modeling techniques to speed-up the simulation speed. The other one is using the cycle accurate modeling to obtain the precisely timing behavior. Designers can use these virtual platforms for either early HW/SW validation or architecture exploration. Therefore, designers can rapidly obtain the performance-TSV relationship with various system architectures based on the proposed virtual platforms. In our work, we analyze different system architectures, mainly the usage of the stacking memory, for our next generation design. We try to explore the maximum performance and the minimum TSVs overhead system architect. Using these ESL techniques can reduce our overall development time a lot for our 3D-PAC design.