Systematic Transistor Sizing of a CNFET-Based Ternary Inverter for High Performance and Noise Margin Enlargement

Mehdi Takbiri,Keivan Navi,Reza Faghih Mirzaee

doi:10.1109/access.2022.3144981

Abstract

Noise and variation are the two major challenges for the reliability of digital circuits, especially multiple-valued logic (MVL) circuits where the entire voltage range is divided into some narrow zones. In spite of few correct examples, many ternary inverters with reduced noise margins have been presented in the literature. The defect is mainly because of their improperly shaped voltage transfer characteristic (VTC). With proper transistor sizing, we can rectify the problem and provide uniformly wide noise margin values while maintaining power-delay product (PDP) low. As far as we know, none of the previous ternary inverters has been given based on a methodical transistor sizing procedure. In this paper, a systematic transistor sizing through physical equations is suggested for an existing standard ternary inverter (STI), whose original sizes for the carbon nanotube FETs (CNFETs) are inappropriate. This paper includes a comprehensive investigation to determine appropriate values for the physical parameters of the CNFET-based STI. Compared with the original design, with a negligible increase in circuit delay and area, simulation results show that the proposed ternary inverter can increase noise margin and static noise margin by up to 47.7% and 83.3%, respectively.

Highlights

Multiple Valued Logic (MVL) has a long history
It consists of a Negative Ternary Inverter (NTI), a Positive Ternary Inverter (PTI), and a couple of voltage dividers (TN3 and TP3, which are constantly ON) to produce the standard ternary output on the basis of (1)
Since the voltage transfer characteristic (VTC) curve is almost divided into three equal parts from the Vin-axis (Fig. 2(b)), noise margins (NMs) values are not uniform, meaning that NM0 and NM2 are 150mV wider than NM1− and NM1+

Summary

INTRODUCTION

Multiple Valued Logic (MVL) has a long history. In 1920, Jan Lukasiewicz began to create the first MVL system. The ternary inverters in [15] and [38] have the same structure The latter has wider NMs because of having transistors with more appropriate sizes. The size of transistors for ternary inverters has previously been determined by the trial and error method with the aim of reducing Power-Delay Product (PDP). We thoroughly discuss the correct size of transistors for one of the previously presented ternary inverters through physical equations.

BACKGROUND

REVIEW OF CNFET TECHNOLOGY

PROPOSED TRANSISTOR SIZING

SIMULATION RESULTS AND COMPARISONS

LIMITATIONS

CONCLUSION AND FUTURE WORKS