Abstract
In this paper, a systematic top-down design method for analog-to-digital converters is presented. Starting at a very high level, with only specifications for the DR, SNDR and bandwidth, the converter architecture is selected, followed by high level simulation. These results are then used in a building-block topology selection step, followed by an automatic sizing step and then intermediate and full transistor-level simulation. It is shown that the systematic flow can lead to faster and more robust design of ADCs, but that next to the top-down design flow a bottom-up modeling flow should be present.
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