Systematic realisation of binary and multivalued logic functions using charge coupled building blocks

Abstract

The suitability of basic CCD gates for the synthesis and realisation of binary and multivalued logic (MVL) functions is now investigated. Systematic design methods for these functions are presented using the proposed building blocks. Characterisation of functions in terms of the type of CCD gates required for their implementation is introduced and used to introduce two functionally complete sets of operations in the charge domain. Use of these operations in the realisation of binary functions is explained and illustrative examples are given. Realisation of some important binary and MVL circuits is also presented. A high-level (macro-cell-like) synthesis approach is proposed for the realisation of functions using CCD building blocks. It does not address circuit-level problems such as charge level degradation, delay synchronisation, layout constraints, etc. Remedies for these problems, using, for example, charge regeneration, charge-to-voltage conversion, etc., may change the cost set up for individual blocks. However, they do not influence the synthesis approaches presented.