System on Chips optimization using ABV and automatic generation of SystemC codes

Abstract

In complex System on Chips (SoCs), system level platforms are built around a set of IPs including processor cores, memories and dedicated hardware (FPGA, ASIC). The better for modeling is using a single system level language during implementation. However, as IPs are in different languages, there is a need to several adaptations and conversion processes, hence making the platforms un-optimized. In this paper we fit the optimization problems by enhancing performances of SystemC SoC platforms according to a treble: productivity, simulation speed and improved verification. We enabled the two first using ST Microelectronics mature techniques and the third with a novel assertion-based verification that we proposed in this paper. As experimentation we used realistic IPs from ST Microelectronics and ARM in order to build the SoC platforms. Among these IPs, some are modeled in VHDL, some other are in Verilog and the rest are in SystemC.