Abstract

In this paper we present an approach for real-time simulation and Hardware-in-the-Loop (HIL) testing of Modular Multilevel Converters (MMCs) that rely on switching models while supporting system level analysis. Using the Latency Based Linear Multistep Compound (LB-LMC) approach, we achieved a 50 ns simulation time step for systems composed of several MMC converters and for converters of various complexity. To facilitate system level testing, we introduce the use of a serial communication-based (Aurora) interface for HIL testing of MMC converters and we analyzed the effect that communication latency has on the accuracy of the HIL test. The simulation and HIL results are validated against an MMC laboratory prototype.

Highlights

  • The combined use of converters with switching devices able to operate at high frequencies—along with the high number of modules used in many Modular Multilevel Converters (MMCs) configurations—produces high apparent switching frequencies that require very small time steps to be accurately simulated

  • For the case of the MMC model validation presented here, xmeas i is a sample of the Csim capacitor voltage minus its average computed over the entire timespan of the simulation, while xre f i, is a sample of the HW MMC capacitor voltage minus its average value computed over the same time span of the Csim

  • In this paper we presented a solution for real-time simulation and Control Hardware In the Loop (CHIL) testing of power electronic systems including switching representation of MMC converters

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Summary

Introduction

Before proceeding with the core of the paper, we provide here a survey of recent developments for system level real-time simulation of power electronics-based power systems and HIL testing, especially of MMCs. Let us first consider simulations with a time step equal to or larger than 5 μs, as those are intended for analysis of large power systems since they are not capable of accurately representing the fast dynamics of high switching frequency converters. Simulations with time step between 5 μs and 500 ns use more detailed models for the switching devices but the size of the system and of the converters is typically smaller than in the previous case This is mainly due to the limited scalability of the approaches involved.

The LB-LMC Method
LB-LMC MMC Model
Hardware Reference System
CHIL Setup
RT Simulation FPGA Implementation
Simulator Interface
Communication Delay Estimation
MMC Model Validation
Scalability Analysis
Communication-Based CHIL Accuracy
Comparison of CHIL and Real Hardware Results
Conclusions
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