An FPGA-based real-time HIL test bench for full-bridge modular multilevel STATCOM controller

Abstract

The modular multilevel converter (MMC) STATCOM removes the need for AC filter and transformer, has no DC bus fault hazard, and thus becomes a better option than a 2-level voltage source converter (VSC) STATCOM. An MMC can have hundreds of submodules (SM). The switches in the SM are controlled individually and the capacitor voltages have to be balanced. Therefore, the control and protection system is sophisticated and has to be validated for different scenarios preferably by hardware-in-the-Loop (HIL) tests. Modeling MMC in detail and simulating it in real time has two main challenges: solving the large circuit containing numerous switches and handling numerous inputs and outputs (IO) in very small time steps. This paper presents a real time test bench, which implements the detailed MMC valve models in field programmable gate array (FPGA) boards and enables connecting to external controllers through high speed protocols used by MMC manufacturers. It can simulate very large systems, e.g. multiple MMC STATCOM and high voltage direct current (HVDC) systems with up to 1000 SM per valve, at multiple sampling rates in real time: the MMC valve is simulated in FPGA with a time step of 250 ns and the rest of the power system is simulated in central processing unit (CPU) cores with a time step of tens of microseconds. The detailed MMC model in the test bench is able to accurately reproduce system behaviors in steady state, transients and faults, which facilitate HIL tests of actual MMC controller for all scenarios in a close-to-reality environment.