System design, optimization and intelligent code generation for standard digital signal processors

Abstract

The architecture of a new code generator for digital signal processors (DSPs) and the motivations for a new high-level specification environment are described. Graphical signal flow graph (SFG) and the Silage language are used as input specifications. Extremely efficient code can be generated for existing commercially available DSP processors. Because of the DSP knowledge embedded in the system, the code generated is about five to 50 times faster than the one produced with conventional C compilers and is comparable to the code generated by DSP experts. The code generator comprises part of a powerful DSP design environment that allows the user to choose a solution based on one or more commercially available DSP processors or to select one of the DSP silicon compilers available in this framework. System-level or bit true software simulators or hardware accelerators can also be called at different stages of the design. >