System aware ESD clamp design for 802.3bt PD PoE controller

Abstract

In this paper we present the development of an electrostatic discharge (ESD) protection supply clamp for an 802.3bt PD PoE controller. Conflicting requirements between chip-level ESD protection and application-level surge requirements are discussed and an appropriate chip-level supply protection scheme is proposed. Chip-level ESD and latch-up (LU) results are reviewed and the role of the ESD supply clamp in a LU failure is discussed. A characterization method for extending the System-Efficient ESD design (SEED) approach to surge pulses is presented and applied to the IC and externals. Finally an application diagram for enhanced surge protection is proposed that enables the PD PoE controller to operate in harsh electrical environments.