Abstract
Synthesis of the vertically aligned carbon nanotubes (CNTs) using complementary metal-oxide-semiconductor (CMOS)-compatible methods is essential to integrate the CNT contact and interconnect to nanoscale devices and ultra-dense integrated nanoelectronics. However, the synthesis of high-density CNT array at low-temperature remains a challenging task. The advances in the low-temperature synthesis of high-density vertical CNT structures using CMOS-compatible methods are reviewed. Primarily, recent works on theoretical simulations and experimental characterizations of CNT growth emphasized the critical roles of catalyst design in reducing synthesis temperature and increasing CNT density. In particular, the approach of using multilayer catalyst film to generate the alloyed catalyst nanoparticle was found competent to improve the active catalyst nanoparticle formation and reduce the CNT growth temperature. With the multilayer catalyst, CNT arrays were directly grown on metals, oxides, and 2D materials. Moreover, the relations among the catalyst film thickness, CNT diameter, and wall number were surveyed, which provided potential strategies to control the tube density and the wall density of synthesized CNT array.
Highlights
Aligned carbon nanotubes (CNTs), which show high conductivity, high thermal stability, and high-mechanical strength [1,2,3], have been intensively studied and employed as the electrodes and interconnects for advanced interconnect applications [4,5,6,7,8]
As a single CNT can provide a high current density close to 109 A/cm2 [5], the CNT array with a wall density more than 1013 cm−2 has been considered as the ideal material for the via interconnect to overcome the electromigration challenges in current complementary metal-oxide-semiconductor (CMOS) technology [9,10,11,12]
Ma et al [32] reported the direct synthesis of CNT array on multilayer MoS2 films, which were transferred onto the SiO2 substrate using mechanical exfoliation
Summary
Aligned carbon nanotubes (CNTs), which show high conductivity, high thermal stability, and high-mechanical strength [1,2,3], have been intensively studied and employed as the electrodes and interconnects for advanced interconnect applications [4,5,6,7,8]. As a single CNT can provide a high current density close to 109 A/cm2 [5], the CNT array with a wall density more than 1013 cm−2 has been considered as the ideal material for the via interconnect to overcome the electromigration challenges in current complementary metal-oxide-semiconductor (CMOS) technology [9,10,11,12]. By using the process of CNT array templating [14], dielectric layers with a recorded low value of 1.75 were achieved [15]. A few reports on the synthesis of CNT on 2D materials are reviewed
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