Synthesis of low power clock trees for handling power-supply variations

Abstract

The International Symposium on Physical Design (ISPD) 2010 contest presents the challenge of synthesizing clock distribution networks that are tolerant to severe power-supply and wire-width variations. In particular, a robust clock network should satisfy the local clock skew (LCS) constraint, i.e., the clock skew between any pair of sequential elements that are closer than a user-specified distance is below a user-specified limit, even in the presence of variations. In this paper, we identify a few factors that help in tolerating these variations in clock trees. Our proposed clock tree router uses a two-stage flow to construct low-power clock trees for which the LCS constraints are met. Our clock tree router has been tested on ISPD'10 contest benchmark circuits. Extensive Monte-Carlo simulations showed that low power clock tree solutions could effectively handle variations, even when we imposed more stringent conditions in the experimental setup.