Improve clock tree efficiency for low power clock tree design

Abstract

Low power design is critical in today's chip design. Clock tree takes much of chip power. “Clock tree cost” is introduced to help design low power clock tree. Five methods are proposed to reduce “clock tree cost” and improve clock tree efficiency. They include clock sink depth check, redundant scan mux check, redundant clock gating cell check, CCOPT (Clock Concurrent Optimization) and simple clock tree, and low threshold voltage tree. By these ways, clock tree efficiency is improved and clock tree power is reduced.