Synthesis from register-transfer level VHDL

Abstract

A description is given of the use of VHDL (VHSIC hardware description language) as a register-transfer-level input language for logic synthesis systems. The register-transfer level is used since effective synthesis algorithms exist at this level. VHDL is used since it is the only standardized hardware description language. Problems arise because VHDL is more oriented to simulation than it is to hardware description. A subset of VHDL is proposed which makes VHDL usable as an input language to synthesis tools. >