Abstract
Quantum processors need to improve their reliability to scale up the number of qubits and increase the number of algorithms that can execute. To reduce the logical error rate of the quantum systems, the use of error correction codes and decoders has been established as a low-cost and feasible approach, with good results from a theoretical perspective, for mid and long-term architectures. While most of the authors are focused on the algorithms to improve the correction capability of quantum computers, without taking into account a fundamental implementation aspect for their deployment in a real system, i.e. , their latency must be bounded to avoid the qubit decoherence, only a few propose hardware architectures and they just include time estimations of their decoding latency. However, a real implementation has not been shown yet. In this work, we analyze from the point of view of hardware implementation two algorithmic options based on quantum low-density parity-check (QLDPC) codes: a) belief propagation min-sum decoders combined with codes with good error-floor behavior and b) belief propagation min-sum decoders concatenated with ordered statistics decoders (OSDs) for codes with early error-floor. The bounds for the maximum clock frequency required by the decoders to decode within the qubit coherence time are established as a parameter to show if a practical implementation is possible with the present or near future FPGA technology. Furthermore, real implementation results for a Xilinx FPGA device are provided, showing that some solutions can meet the timing constraints set up by the state-of-the-art quantum processors.
Highlights
Q UANTUM error correction codes have been deeply studied for more than three decades [1], [2], [3]
To perform the implementation and set up a lower boundary, the (255,32) quantum low-density parity-check (QLDPC) code was selected, as: i) it is the one with more restrictive parameters, from the hardware point of view and; ii) it is one of the codes with better error correction capacity
The code parameters, M=112, dc=10 and dv =5 are representative to evaluate the routing congestion of the design and compute a realistic fmax, limited by the logic involved in the critical path and by the wiring, which can be used as a reference for the implementation of other simpler QLDPC codes
Summary
Q UANTUM error correction codes have been deeply studied for more than three decades [1], [2], [3]. Different decoding algorithms based on techniques like Blossom decoder [9], message-passing [10] and artificial intelligence (neural-networks) [11] have been described showing the benefits and the error-correction capacity of each method Even though these codes and decoders show several orders of magnitude of improvement of the output error rate of the quantum processors, from theoretical analysis, most of the solutions do not provide physical implementations and it remains unclear that if in a real system these solutions are fast enough to handle with the qubit decoherence (which is the perturbation of the superposition states of the qubits by their interaction with the environment) [12]. The main differences of both classical and quantum decoders can be seen in the block diagrams from Fig.
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