Synchronous Real-Time Sampling Technique for Side-Channel Analysis Against Randomly Varying Clock-Based Countermeasures

Hyemin Yang,Changkyun Kim,Eun-Gu Jung

doi:10.1109/access.2021.3103183

Abstract

Power analysis attacks pose a significant threat to the security of cryptographic devices as they can reveal a secret key. Performing cryptographic operations based on a randomly varying clock (RVC) is a practical countermeasure against such attacks. The countermeasure makes it difficult to align power traces, which is a prerequisite for power analysis attacks to succeed. This paper introduces a synchronous real-time sampling (SRTS) technique as an advanced hardware-implemented approach to collect traces for a power analysis attack that negates countermeasures involving practical RVCs. By recovering the RVC, the leakage signal corresponding to the recovered clock edge is synchronously sampled in real time. We propose an analog-based hardware system implemented with two circuit blocks for SRTS operations, namely, a clock recovery block and an analog signal-processing block. The target of the power analysis attack is an Advanced Encryption Standard (AES)-128 software-implemented smart card operated at 20 MHz, which is varied in the range of 30% by the RVC countermeasure. The traces captured by the SRTS show that the suboperations of the AES encryption are distinct in contrast to the indistinguishable waveforms captured at a fixed sample rate. The results of the power analysis attack demonstrate that the correct key is successfully extracted with a high correlation coefficient at the S-box output of the AES. The proposed SRTS method improves the relative distinguishing margin by 191.4% and reduces the required number of traces to 2.75% compared with the conventional correlation power analysis attack with a fixed sample clock.

Highlights

Cryptographic devices implemented in hardware inevitably leak secret information due to unintended physical phenomena resulting from acoustic, thermal, optical, power, and electromagnetic effects [1], [2]
We introduced the synchronous real-time sampling (SRTS) technique, as an advanced tracecollecting method, for a hardware-based power analysis attack that negates countermeasures of a trace misalignment based on an randomly varying clock (RVC)
The target for the power analysis attack was the Advanced Encryption Standard (AES)-128 software-implemented smart card that applied the countermeasure with a RVC operated within a 30% bandwidth with respect to a 20 MHz operating frequency

Summary

Introduction

Cryptographic devices implemented in hardware inevitably leak secret information due to unintended physical phenomena resulting from acoustic, thermal, optical, power, and electromagnetic effects [1], [2]. Since Kocher et al [8] first introduced differential power analysis (DPA) in 1999, and since Brier et al [9] introduced correlation power analysis (CPA) in 2004, the risk of exposing cryptographic keys by collecting and analyzing leakage power signals from hardware devices has existed. DPA and CPA have been successfully used to retrieve secret information by modeling side-channel leakages with Hamming weight and Hamming distance models [8]–[11]. A CPA attack employs Pearson’s correlation coefficient to evaluate the linear relationship between the measured power traces and hypothetical power consumption values [10]. The most commonly used power models are the Hamming-weight and Hamming-distance models used to obtain hypothetical power consumption values. The correlation coefficient (ρ) between the Hamming weight matrix (H) and the obtained power traces (T ) can be given as

Methods

Results

Conclusion