Switching Activity Reduction in Graphene PN Junction Circuits using Circuit Re-structuring

Abstract

Graphene PN Junction (GPNJ) logic circuits received significant attention from the researchers thanks to the availability of electrostatically doped graphene PN Junction (GPNJ) device- a promising one for designing low-power, high-speed circuits. Several design approaches for GPNJ logic circuits realizing important arithmetic and arbitrary Boolean functions exist in literature. However, no detailed evaluations of the resulting circuit complexities with respect to relevant cost metrics are reported. It remains open, how do we synthesize GPNJ logic circuits with minimal switching activity, an essential cost metric influencing the dynamic power dissipation in the resulting circuits. In this paper, we introduce a synthesis approach for GPNJ logic circuits that interconnects a set of GPNJ devices in parallel. Such parallel circuit structures ensure the reduction of switching activity in the resulting GPNJ logic circuits. To the best of our knowledge, so far only one research work discussed the computation of switching activity of GPNJ logic circuits. Experimental evaluations confirm that an average 67.35% reduction in switching activity can be achieved using the proposed approach over the existing one.