Abstract
In this paper, a very low voltage low power high resolution pipelined ADC is presented. Several challenges in very low voltage high resolution ADC design are addressed and a low-power design methodology for switched-opamp (SO) converters is presented. This methodology determines the optimum values of all capacitors, including the compensation capacitors of the opamps and also the stage resolutions that will lead to minimum power consumption for a specified value of signal-to-noise ratio. For a 12-bit ADC, a novel 2.5-bit first stage is followed by eight 1.5-bit stages and a 2-bit back-end flash ADC. Design considerations and simulation results of the 12-bit 1-V 10MS/s pipelined SO ADC with low power consumption are also presented.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
