Abstract
In this paper, a very low-voltage low-power high-resolution pipelined ADC is presented. Several challenges in very low voltage high resolution ADC design are addressed and a low-power design methodology for swithched-opamp (SO) converters is presented. This methodology determines the optimum values of all capacitors, including the compensation capacitors of the opamps and also the stage resolutions that will lead to minimum power consumption for a specified value of signal-to-noise ratio. A novel 2.5-bit stage is also presented. Design considerations and simulation results of the 12-bit 1-V 10-MS/s pipelined SO ADC with low power consumption are addressed. The effective number of bits is 11.2 for a 1-MHz 1.2V/sub p-p,diff/ input signal.
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