Switch-Level Logic Simulation of Digital Bipolar Circuits

Abstract

This paper describes a new approach for logic simulation of bipolar digital circuits. The approach is based on the development of a switch-level model of the transistor and on representing the circuit by a switch-graph. The method automatically partitions the circuit into subcircuits, and symbolic logic expressions are then generated which represent the logic states of the nodes in terms of subcircuit inputs and initial conditions. The method thus extracts a gate-level functional description of the circuit from transistor netlist or layout. Logic and fault simulation can then be performed using either extracted logic expressions or the switch-graph model. The approach has been implemented in a computer program for logic simulation of common-mode logic (CML) bipolar circuit designs.