Delay modeling and timing of bipolar digital circuits

Abstract

An approach for timing simulation of bipolar ECL (emitter-coupled-logic) digital circuits is described. The approach is based on the development of a switch-level model of the transistor and on the representation of the circuit by a switch graph. The circuit is partitioned into subcircuits, and symbolic logic expressions are generated which represent the logic states of the nodes in terms of subcircuit inputs and initial conditions. Timing information is computed using an analytical delay model which relates outputs of a subcircuit to its input waveforms. The model includes the effects of the transistor SPICE parameter model as well as the circuit parameters. The combination of the switch-level graph model and the delay model provides fast and accurate timing simulation of ECL circuits. In addition, the switch-graph model provides a unified way for simulating BIMOS circuits. >