Abstract
In this paper, an integrated variability and reliability analysis method based on surrogate models is introduced. The surrogate models here are response surfaces that describe a parametrized complex analytic function. Surrogate models are developed for the drain currents of 65-nm NMOS and PMOS devices in terms of critical process components, terminal voltages, temperature, and time and are based on BSIM model equations. A simulation technique is developed which incorporates the effect of process variations into the design procedure. These models and techniques are verified using circuit simulations of a single transistor and differential amplifier designs.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: IEEE Transactions on Device and Materials Reliability
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
