Surface Tunnel Transistor: Gate-Controlled Lateral Interband Tunneling Device

Abstract

We demonstrated a novel three-terminal tunnel device, the Surface Tunnel Transistor (STT), in which lateral interband tunneling current between source and drain is controlled by a gate voltage. The STT consists of a highly degenerate drain whose polarity is opposite that of the source, a channel with an insulated gate, and a source connected to the channel. The basic characteristics of the STTs were investigated by fabricating three types of STTs with mesa structures using a GaAs/AlGaAs system, as well as by a two-dimensional device simulation. An enhancement-type STT (E-STT) in which no electrons are accumulated on the channel surface at thermal equilibrium exhibited unsaturated transistor characteristics due to interband tunneling under source-drain reverse bias conditions. To increase the current density, a modulation doped STT (MD-STT) in which the channel was formed by modulation doping was also fabricated, and a tunneling current about 104 times larger than that of the E-STT was obtained. Moreover, the MD-STT showed negative differential resistance (NDR) characteristics under source-drain forward bias conditions. A channel doped STT (CD-STT) in which the channel region was directly doped with donors showed improved NDR characteristics with a peak current density of 3.7 µA/µm and a peak-to-valley current ratio (PVR) of 1.5 at room temperature. These values are larger than those of the MD-STT by a factor of 103 and 1.5, respectively. Furthermore, a PVR as high as 4.8 was obtained for the CD-STT by inserting a blocking layer between the drain and the overlapped channel layer to reduce the valley current.