Abstract
A surface potential-based model for embedded flash memory cells has been developed with the purpose of providing a comprehensive physical understanding of the device operation suitable for performance optimization in memory circuit design. The device equations account for charge balance effects on the isolated floating gate node and parasitic couplings between the terminals of the memory cell. The compact model supports DC, AC and transient analyses, including program/erase bias scalability, drain disturb and memory endurance degradation due to oxide aging. After validation, the model has been applied to parametric analysis and used to evaluate critical trade-offs in memory design.
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