Surface cleaning of small structures during spin rinsing of patterned substrates

Abstract

A comprehensive process model for rinse process in tools is presented.Process model used to develop new rinse recipes for hafnium-based patterned wafers.Key process parameters: speed of rotation, flow rate, and wafer size are studied.Determined the bottleneck of the rinse process to minimize the water usage. Cleaning and rinsing of small structures are important processes in the manufacturing of micro- and nano-electronics. The latest technology uses single-wafer spin rinsing'' in which ultra-pure water (UPW) is introduced onto the wafer which is mounted on a rotating holder. This is a complex process and its optimization for lowering water and energy usage requires better understanding of the process fundamentals. A mathematical model is presented in this paper that uses the fundamental physical mechanisms and provides a comprehensive process simulator. The model includes fluid flow, electrostatic effects, and bulk and surface interactions. The simulator is applied to the specific case of investigating the dynamics of rinsing of patterned wafers with hafnium-based high-k micro- and nano-structures. The effects of key rinse process parameters such as water flow rate, wafer spin rate, water temperatures, wafer sizes, and trench locations in the wafer are studied. Successful incorporation of this rinsing simulator in design and control of surface preparation processes would eliminate dependence on costlier and more time-consuming external analysis techniques.