Abstract
Approaches used to suppress the hot-carrier effects in submicrometer CMOS technology based on the drain engineering of the device structure and process-induced deice degradation are discussed. Different types of lightly doped drain (LDD) structures are studied. Several process-related device aging issues are discussed. Twin-Tub V CMOS technology is used as an example of how to manage the hot-carrier issues with respect to the process integration aspects. >
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