Suppression of DIBL in deca-nano SOI MOSFETs by controlling permittivity and thickness of BOX layers

Abstract

The Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) fabricated on a Silicon-On-Insulator (SOI) substrate is effective to suppress Short Channel Effect (SCE), and is one of the most promising electron devices for Very Large Scale Integration (VLSI) circuits for higher speed, higher integration density, and lower power consumption, and it has been already demonstrated that SCE in deep submicron SOI MOSFETs comes from Drain-Induced Barrier Lowering (DIBL) at SOI/Buried OXide (BOX) interface by the author's group. This paper elucidates the roles of permittivity and thickness of BOX layers in suppressing the DIBL in SOI MOSFETs by performing numerical device simulations of SOI MOSFETs with various permittivity and thickness of BOX systematically and by visualizing distribution of dielectric flux lines and current flow lines as well as contour potential lines in MOSFETs.