Abstract
Page migration has long been adopted in hybrid memory systems comprising dynamic random access memory (DRAM) and non-volatile memories (NVMs), to improve the system performance and energy efficiency. However, page migration introduces some side effects, such as more translation lookaside buffer (TLB) misses, breaking memory contiguity, and extra memory accesses due to page table updating. In this paper, we propose superpage-friendly page table called SuperPT to reduce the performance overhead of serving TLB misses. By leveraging a virtual hashed page table and a hybrid DRAM allocator, SuperPT performs address translations in a flexible and efficient way while still remaining the contiguity within the migrated pages.
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