Abstract
This paper presents a time-to-digital converter (TDC) architecture with reduced hardware suitable for multichannel timing built-out self-test (BOST) implementation on an FPGA chip. In order to reduce the number of buffers and DFFs in a conventional Flash TDC or Vernier TDC, successive approximation is applied to construct a SAR TDC when two timing inputs are repetitive (not shingle-shot). Besides, Vernier TDC has been added as the sub-circuit to form a two-step SAR+SAR-Vernier TDC architecture. LTspice and Xilinx ISE simulation have been performed to verify its feasibility. Also discussions on several TDC architectures as BOST are described.
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