Abstract
This paper presents a time-to-digital converter (TDC) architecture with reduced hardware suitable for timing built-in self-test (BIST) / built-out self-test (BOST) implementation. In order to reduce the number of buffers and D Flip-Flops (DFFs) in a conventional Flash TDC or Vernier TDC, successive approximation is applied to construct a successive approximation register (SAR) TDC. Besides, Vernier TDC has been added as the sub-circuit to form a (two-step SAR) + (SAR-Vernier) TDC architecture. Its self-calibration method for the linearity improvement is shown. We also propose to use a trigger circuit (originally used in an equivalent-time sampling oscilloscope) in front of the SAR TDC which enables to measure the timing effectively when two timing inputs are single-shot as well as repetitive clocks.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
