Subthreshold timing error detection performance analysis

Abstract

Timing error detection (TED) is a method in which setup timing errors are detected during run-time. When a violation is found, the system reacts on it to prevent error propagation. Incorporating TED circuits to a design introduces overhead. Thus, understanding how to efficiently implement TED with respect to the design constraints is a key issue. In this paper we compare energies of a conventional design to a TED design using different logic styles with different logic imbalances to investigate the energy difference between the designs in subthreshold operation region. TED mitigates variation problems introduced by using subthreshold operation, which is discussed. Using a 65 nm CMOS process, four different blocks have been simulated and analyzed, and subthreshold energy curves based on the forementioned are presented. The results indicate possibility for energy saving by utilizing TED.