Substrate Noise suppression Techniques for Systems on Chip

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As System-on-Chip designs are becoming popular, the substrate noise topic has attracted much attention in the past. Even today, a significant research effort is devoted to mitigate the impact of mostly digitally generated substrate noise on sensitive mixed-signal circuits. In mixed-signal circuits, complex and noisy digital circuits are integrated on the same substrate with noise-sensitive analog circuits. In fact, it is possible for the noise-inducted currents injected into the common substrate, to result in operational/functional failures of the analog and digital blocks. For example, suppose that we have DSP block, which is switching very fast in the vicinity of a broadband receiver. We can observe that there are some unwanted frequency components with considerable magnitude in the receiver spectrum due to substrate noise degrading the performance. From designers' perspective, one would like to find circuit and physical level techniques to protect sensitive circuits from substrate noise effects. This tutorial covers brief introduction to substrate noise sources and effects, then gives more details about existing substrate noise reduction techniques in two different categories: i) circuit-level, ii)physical level following by discussion on results of scaling on substrate noise and conclusion at the end.